In most advanced complementary metal-oxide semiconductor (CMOS) non-volatile memory, hafnium oxide is used as a gate dielectric. Hafnium oxide has a propensity to form oxygen vacancies, where charge trapping produces threshold-voltage (Vt) shifts. A multiple-time programmable read only memory (MTPROM) uses this charge trapping and charge de-trapping behavior in n-type metal-oxide semiconductor field effect transistors (NMOS FET) to store and erase a bit.
To maximize the Vt detection, a memory cell uses a pair of complement NMOS transistor (NMOSc) and true NMOS transistor (NMOSt). In order to store binary data (i.e., “0” and “1”), charge is trapped at the NMOSc and NMOSt gate dielectric of the respective pair. This twin cell approach minimizes sensitivity to Vt fluctuations due to lot, wafer, chip location, and maximizing a differential bit-line voltage (DBL) for sense (i.e., read state).
A NOR-type array is controlled by word-lines (WLs), bit-lines (BLs), and source-lines (SLs) for programming (i.e., charge trapping), reading (i.e., sensing), and resetting (i.e., charge elimination). In the NOR-type array, SLs are common lines which form a meshed source-line network (MSLN) through the entire NOR-type array. As an example, the NOR-type array may be organized as 256 rows and 256 columns, which results in 64 kilobyte density. The rows are controlled by word line (WL) drivers to activate one of the 256 rows for the programming and read modes. A number of parallel writes are fully and flexibly controlled by the WL drivers from 1 to 256 columns at the same time. This flexibility allows parallel write efficiency and the ability to detect each of the NMOS cell's ON current (ION) characteristics by enabling only one out of 64 kilobytes×2 NMOSs. Thus, in the read mode, 64 out of 256 columns are selected by a column select line (CSL). Each CSL is configured in a manner so as to enable reading 64 bits simultaneously.